This invention relates, in general, to Electrically Erasable Programmable Read Only Memories (EEPROM), and more particularly, to an erase circuit for a CMOS EEPROM which does not use depletion type transistors.
In the past, it has been common practice to use depletion type transistors as controllable coupling transistors to couple a high voltage to the control gate of an electrically erasable memory cell. A depletion type transistor is capable of coupling essentially the total voltage from its drain to its source when the transistor is enabled. In order to render a depletion type transistor non-conductive, a negative voltage must be applied to its gate electrode. However, if zero volts is applied to the gate electrode of a depletion type transistor, it will be rendered partially non-conductive. Such characteristics of the depletion type transistor have rendered themselves very useful for coupling an erase voltage to the control gate of an electrically erasable memory cell. Since a high voltage is needed as the erase voltage, the depletion type transistor is very useful for coupling the high voltage. On the other hand, when the memory cell is not being erased it is desirable to keep its control gate from floating and therefore by applying zero volts to the gate electrode of the depletion type coupling transistor, the control gate is kept from floating.
A problem arises when an EEPROM is manufactured using a CMOS process. To make a depletion type transistor in a CMOS process would entail additional process steps which are undesirable because of the added time and expense involved.
Accordingly, it is an object of the present invention to provide an erase circuit for an EEPROM which does not use depletion type transistors.
Another object of the present invention is to provide an erase circuit for an EEPROM which uses only enhancement type transistors.